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ics for communications multipoint switching and conferencing unit - attenuation musac-a peb 2445 version 1.2 data sheet 02.96
edition 02.96 this edition was realized using the software system framemaker a . published by siemens ag, bereich halbleiter, marketing- kommunikation, balanstra?e 73, 81541 mnchen ? siemens ag 1996. all rights reserved. attention please! as far as patents or other rights of third parties are concerned, liability is only assumed for components, not for application s, processes and circuits implemented within components or assemblies. the information describes the type of component and shall not be considered as assured characteristics. terms of delivery and rights to change design reserved. for questions on technology, delivery and prices please contact the semiconductor group offices in germany or the siemens compa nies and representatives worldwide (see address list). due to technical requirements components may contain dangerous substances. for information on the types in question please cont act your nearest siemens office, semiconductor group. siemens ag is an approved cecc manufacturer. packing please use the recycling operators known to you. we can also help you C get in touch with your nearest sales office. by agreeme nt we will take packing material back, if it is sorted. you must bear the costs of transport. for packing material that is returned to us unsorted or which we are not obliged to accept, we shall have to invoice you for an y costs in- curred. components used in life-support devices or systems must be expressly authorized for such purpose! critical components 1 of the semiconductor group of siemens ag, may only be used in life-support devices or systems 2 with the express written approval of the semiconductor group of siemens ag. 1 a critical component is a component used in a life-support device or system whose failure can reasonably be expected to cause the failure of that life-support device or system, or to affect its safety or effectiveness of that device or system. 2 life support devices or systems are intended (a) to be implanted in the human body, or (b) to support and/or maintain and sust ain hu- man life. if they fail, it is reasonable to assume that the health of the user may be endangered. peb 2445 revision history: current version: 02.96 previous version: digital switching and conferencing ics data book 01.94 page (in version 01.94) page (in new version) subjects (major changes since last revision) 220 11 version 1.2 220 11 p-dip-40 package not further available 224, 227, 243 16, 19, 36 motorola mode not available 249 40 figure (initializing the ? 4096-khz device clock) corrected C 56 abs. max. ratings: i lpd defintion 59 t wd min. = 20 ns 59 t s min. = 15 ns 60 t ss8 min. = 20 ns, t sh4 max. = t cp4 - 10 ns + t cp4h C60 t spl min . = 100 ns added C 66 appendix: design sheets added
peb 2445 table of contents page semiconductor group 3 02.96 1overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 1.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 1.2 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 1.3 pin definitions and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 1.4 functional symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 1.5 device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 1.6 system integration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 2 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 2.1 basic functional principles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 2.2 microprocessor interface and registers . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 3 operational description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 3.1 reset state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 3.2 initialization procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 3.3 operation with a 4096-khz device clock . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 3.4 standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 4 detailed register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 4.1 mode register (mod) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 4.2 status register (sta) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 4.3 conference status register (cst) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 4.4 conference mask register (cmr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 4.5 indirect access register (iar) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 4.6 indirect registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 4.6.1 configuration register (cfr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 4.6.2 clock shift register (csr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 5 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 5.1 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 5.2 capacitances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 5.3 ac-characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 5.3.1 microprocessor interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 5.3.1.1 intel bus mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 5.3.2 pcm interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 5.3.3 clock and synchronization timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
peb 2445 table of contents page semiconductor group 4 02.96 6 package outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 7 appendix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66 7.1 initialization for conferencing in a pbx . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66 7.2 programming a conference in a pbx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 7.3 programming procedure for switching tss . . . . . . . . . . . . . . . . . . . . . . . . .68 7.4 programming procedure for a pbx conference . . . . . . . . . . . . . . . . . . . . . .69 iom ? , iom ? -1, iom ? -2, sicofi ? , sicofi ? -2, sicofi ? -4, sicofi ? -4c, slicofi ? , arcofi ? , arcofi ? -ba, arcofi ? -sp, epic ? -1, epic ? -s, elic ? , ipat ? -2, itac ? , isac ? -s, isac ? -s te, isac ? -p, isac ? -p te, idec ? , sicat ? , octat ? -p, quat ? -s are registered trademarks of siemens ag. musac ? -a, falc ? 54, iwe ? , sare ? , utpt ? , asm ? , asp ? are trademarks of siemens ag. purchase of siemens i 2 c components conveys a license under the philips i 2 c patent to use the components in the i 2 c-system provided the system conforms to the i 2 c specifications defined by philips. copyright philips 1983.
semiconductor group 5 02.96 peb 2445 overview 1overview a complete family of efficient solutions if the issue is digital switching and conferencing, the solution is flexibility, capacity, and economy. siemens semiconductor offers the most economical answer to all conceivable applications in this field. our complete family of switching network devices satisfies even the most rigorous switching demands. a complete family of efficient solutions take our mtsc (memory time switch cmos) peb 2045 with a switching capability of 512 incoming pcm channels to 256 outgoing pcm channels. it has the perfect size to economically build medium sized switches. the design of a non-blocking switch for 512 pcm channels is possible with a simple parallel configuration with a second mtsc. if you need a non-blocking switch for up to 256 channels, we offer a smaller version of the mtsc, the mtss (memory time switch small) peb 2046 . and the mtsl (memory time switch large) peb 2047 , the largest in our family, is capable of switching 1024 pcm channels. siemens also supplies the best solution for conferencing, our musac (multipoint switching and conferencing unit) peb 2245 performs the complete switching functions of the mtsc, and offers a signal processor for handling up to 64 conferencing channels in any combination. the input and output channels can also be attenuated individually to achieve best transmission quality. the musac-a (multipoint switching and conferencing unit) peb 2445 is an upward compatible device to the mtsc and musac. it offers in addition the attenuation and amplification of every time slot. pin compatible device allow simplicity in hardware and software design. to allow for more flexibility, the pcm data rate can be 2, 4, or 8 mbit/s C configurable also for mixed use.
semiconductor group 6 02.96 peb 2445 overview the figure below shows the general architecture of a digital exchange. figure 1 general exchange architecture system background digital exchanges put calls through by newly arranging the speech signals coded with 8-bit words (pcm time-slots). the code words are transmitted serially on pcm lines. the sampling frequency of 8 khz produces pcm frames with a duration of 125 m s. the transmission rate on the line determines how many code words (speech channels) can be accommodated within a sampling period. with a data rate of 2048 kbit/s for example, there are 32 time-slots of 8 bits each. 4 lines with a data rate of 8192 kbit/s have a transmission capacity of 512 channels.
peb 2445 overview semiconductor group 7 02.96 an overview on the complete switching and conferencing ic-family is shown in the following table: table 1 complete switching and conferencing ic family mtsc peb 2045 mtss peb 2046 mtsl peb 2047 mtsl 16 peb 2047-16 musac peb 2245 musac-a peb 2445 epic-1 peb 2055 epic-s peb 2054 switching capacity (time-slots) 512 256 256 256 1024 512 1024 1024 512 256 512 256 256 256 256 256 input/output lines 16/8 8/8 16/8 16/8 16/8 16/8 8/8 sld/iom/ pcm 6/6 iom/pcm pcm-data rate (mbit/s) 2/4/8 + mixed mode 2 2/4/8 + mixed mode 2/4/8/16 + mixed mode 2/4/8 + mixed mode 2/4/8 + mixed mode up to 8 up to 8 clock rate (mhz) 4.096 8.192 4.096 8.192 4.096 8.192 4.096/8.192 16.384 4.096 8.192 4.096 8.192 up to 8.192 up to 8.192 conferencing 64 channels 64 channels attenuation 64 channels 3/6/9 db all channels C 4 to 12 db pri/t1 mode yes yes yes fractional t1 data bundling yes yes 128-kbit/s channel 128-kbit/s channel m c access read read yes yes multipoint switching yes yes power (mw) max. consumption typ 50 50 100 170 100 100 50 50 package p-dip-40 p-lcc-44 p-dip-40 p-lcc-44 p-lcc-44 p-lcc-44 p-lcc-44 p-lcc-44 p-lcc-44 p-lcc-44 1) in definition
semiconductor group 8 02.96 peb 2445 overview conferencing an important task in pcm voice handling is conferencing. i.e. several subscribers of a digital pbx system would like to arrange a conference call. this task will be done in the central switching network. modern switching ic like the musac-a fulfill this important task in a cost effective way in the central switching unit. a powerful on chip digital signaling processor handles this requirement. definite time-slots will be added together to one subscriber signal. in order to ensure an acceptable speech quality and reduce of echo and singing problems, the input and output channels have to be attenuated individually. additionally, input signals below a threshold programmable to different levels are disregarded. another trick to lessen the risk of instability in multiparty conferences is to invert every second voice channel. odd and even channels are substracted from one other. conferencing with the musac tm -a conferencing means that pcm data of several subscribers are processed such that each subscriber receives the contribution of the pcm data transmitted by all participants of the conference. except the data transmitted by himself. each subscriber is qualified by an input channel which corresponds to a certain input line and time-slot of the musac-a, and an output channel which corresponds to a certain output line and time-slot of the musac-a. the data flow through the musac-a in case of conferencing is illustrated in figure 2 .
semiconductor group 9 02.96 peb 2445 overview figure 2 data flow through the musac-a in case of conferencing
peb 2445 overview semiconductor group 10 02.96 the pcm samples of each input channel first pass through an input processing stage. in this stage, an input attenuation level (0, 3, 6 or 9 db) and a noise suppression threshold can be programmed individually for each channel. following the input processing the pcm data is expanded according to the a- or m -law encoding rules and written to the data memory (dm). additionally the pcm data of each input channel is added to the conference sum memory (csm). the dm location (1 out of 64) is specified by the conference control address (cca) and the csm location (1 out of 21) is specified by the conference number when writing to the conference control memory (ccm). the pcm data then passes through a substractor stage such that the resulting output channel for a given subscriber contains the contribution of all the other channels in the conference except its own. finally the pcm data is forwarded to the output channel after pcm compression and an optional output attenuation of 3 db. attenuation attenuation is a new requirement for pbx switching systems. the purpose is to avoid echo and noise problems on a pbx network for voice connections with access to the public network. further a certain loudness rating on a definite point for different terminals and phones could be fixed (see figure 3 ). figure 3
p-lcc-44 semiconductor group 11 02.96 multipoint switching and conferencing unit - attenuation musac tm -a peb 2445 version 1.2 cmos ic type version ordering code package peb 2445-n v1.2 Q67100-H6298 p-lcc-44 (smd) 1.1 features switching ? time/space switch for 2048-, 4096- or 8192-kbit/s pcm systems ? switching of up to 512 incoming pcm channels to up to 256 outgoing pcm channels ? 16 input and 8 output pcm lines ? different kinds of modes (2048, 4096, 8192 kbit/s or mixed mode) ? configurable for a 4096- and 8192-khz device clock ? tristate function for further expansion and tandem operation attenuation and amplification ? attenuation and amplification of every time-slot ? attenuation range from 0 to 12 db ? amplification range from 0 to 4 db
peb 2445 overview semiconductor group 12 02.96 conference mode ? up to 64 conference channels in any combination ? up to 21 independent conferences simultaneously (3 subscribers) ? programmable attenuation (0/3/6/9 db) on each input channel ? programmable attenuation (0/3 db) on each output channel ? programmable pcm-level adaption (attenuation or amplification) of up to 64 channels ? programmable noise suppression (four thresholds) ? conference overflow handling ? tone insertion capability ? a-law / m -law compatible ? compatible with all kinds of pcm-byte formats multipoint switching ? multiple independent lans within one pbx ? multiplexing of up to 64 channels ? 64-kbit/s channels general ? 8-bit m p interface ? single + 5 v power supply ? advanced low power cmos technology ? ttl-compatible inputs/outputs ? upward compatible to mtsc and musac general description the musac-a is an upward compatible device to the reliable components mtsc and musac. additionally to the standard musac features switching and conferencing, the musac-a supports enlarged attenuation functions. every time-slot is freely programmable in 1-db step resolutions to an attenuation range from 0 to 12 db and amplified from 0 to 4 db. with enlarged attenuation functions to every time-slot the musac-a fulfills the ability for new requirements. i.e. different pbx terminals could be adapted to a certain reference point from the private network to the public network.
peb 2445 overview semiconductor group 13 02.96 1.2 pin configuration (top view) p-lcc-44
peb 2445 overview semiconductor group 14 02.96 1.3 pin definitions and functions pin no. p-lcc symbol input (i) output (o) function 1 v ss i ground (0 v) 6int od open drain interrupt request: the signal is activated when a conference overflow is detected. the microproces- sor may determine the specific conference in over- flow by reading the conference status register (cst). the interrupt is maskable. int is an open drain output, thus a wired-or combination of inter- rupt request outputs of several musac-as is pos- sible (a pull up resistor is necessary). 3sp i synchronization pulse: the musac-a is syn- chronized relative to the pcm system via this line. 4 7 9 11 13 14 15 16 17 18 19 in1 in5 in9 in13 in14 in15 in10 in11 in6 in7 in2 i i i i i i i i i i i pcm-input ports: serial data is received at these lines at standard ttl levels. 5 8 10 12 in0/tsc0 in4/tsc1 in8/tsc2 in12/tsc3 i/o i/o i/o i/o pcm-input port / tristate control: in standard configuration these pins are used as input lines, in primary access configuration they supply control signals for external devices. 20 in3/dcl i/o pcm-input port / data clock: in standard config- uration in3 is the pcm-input line 3, in primary access configuration it provides a 2048-khz data clock for the synchronous interface. 21 28 a0 a1 i i address for direct register access: these pins are only active if a demultiplexed m p-interface mode is selected. if a1 is not connected it will be set to ground inter- nally.
peb 2445 overview semiconductor group 15 02.96 22 cs i chip select: a low level selects the musac-a for a register access operation. 23 v dd i supply voltage: 5v 5% 24 rd i read: this signal indicates a read operation and is internally sampled only if cs is active. the musac-a puts data from the selected internal reg- ister on the data bus with the falling edge of rd . rd is active low (siemens/intel bus mode). 25 wr i write: this signal initiates a write operation. the wr input is internally sampled only if cs is active. in this case the musac-a loads an internal regis- ter with data from the data bus at the rising edge of wr . wr is active low (siemens/intel bus mode). 2ale i address latch enable: in the intel type multi- plexed m p-interface mode a logical high on this line indi- cates an address of a musac-a internal register on the external address/data bus. in the intel type demultiplexed. m p-interface mode this line is hardwired to v ss , in the demultiplexed motorola type m p-interface mode it should be connected to v dd . if ale is not connected it will be set to ground inter- nally. 26 27 29 30 31 32 33 34 ad0 ad1 ad2 ad3 ad4 ad5 ad6 ad7 i/o i/o i/o i/o i/o i/o i/o i/o address data bus: if the multiplexed address/data m p-interface bus mode is selected these pins transfer data and addresses between the m p and the musac-a. if a demultiplexed mode is used, these bits inter- face with the system data bus. 1.3 pin definitions and functions (contd) pin no. p-lcc symbol input (i) output (o) function
peb 2445 overview semiconductor group 16 02.96 35 36 37 38 40 41 42 43 out7 out6 out5 out4 out3 out2 out1 out0 o o o o o o o o pcm-output port: serial data is sent by these lines at standard cmos- or ttl levels. these pins can be tristated. 39 res i reset: a high signal on this input forces the musac-a into reset state. the minimum pulse length is four clock periods. if this pin is not con- nected it will be set to ground internally. 44 clk i clock: 4096- or 8192-khz device clock 1.3 pin definitions and functions (contd) pin no. p-lcc symbol input (i) output (o) function
peb 2445 overview semiconductor group 17 02.96 1.4 functional symbols figure 4 functional symbol for the standard configuration figure 5 functional symbol for the primary access configuration
peb 2445 overview semiconductor group 18 02.96 1.5 device overview the multipoint switching and conferencing unit (musac-a) combines a time switch unit (mtsc) and a powerful signal processor on one chip. the musac-a enhances the capabilities of a pbx by supporting teleconferencing and multipoint data communication over voiceband channels. digital signal processing techniques are used to implement the conferencing algorithms. up to 64 channels of the 512 incoming pcm channels may be manipulated by the signal processor and output to any of 256 outgoing pcm channels. all functions are programmed and controlled via an 8-bit standard m p interface (intel type). the musac-a is fabricated using the advanced cmos technology from siemens and is mounted in a p-lcc-44 package. inputs and outputs are ttl-compatible. the peb 2445 is pin and register compatible to the peb 2045. in addition, it includes the following features: ? conference unit ? programmable attenuation for each output channel in the range of - 4 db up to 12 db. ? the attenuations of the outputs and the attenuations in the conference unit can be selected independent of one another. figure 6 block diagram of the peb 2445
peb 2445 overview semiconductor group 19 02.96 1.6 system integration conferencing the musac-a is designed to connect any of the 512 pcm-input channels to any of 256 output channels. any input channel up to a total number of 64 can be handled in 21 independent conferences simultaneously. any conference combination from 3 subscribers in 21 conferences up to 64 subscribers in only one conference is possible. in order to ensure an acceptable speech quality and to reduce echo and singing problems, the input channels can be attenuated individually by 0, 3 db, 6 db or 9 db and the output channels by 0 or 3 db; additionally, input signals below a threshold programmable to four different levels are disregarded (see chapter 4.5 ). to lessen the risk of instability in multiparty conferences the voice signal from every second channel can be inverted so that disturbance signals in odd and even channels are subtracted from one another. if more capacity is needed, several devices can be connected. by connecting the 16 pcm-input lines in parallel to two musac-as, a non-blocking switching matrix for 512 subscribers can be implemented: 128 input channels can be selected for up to 42 independent, simultaneous conferences. figure 7 shows such an arrangement. due to the tristate capability of the musac-a larger switches with conferencing capability can be easily formed. figure 7 memory time switch 16/16 for a non-blocking 512 channel switch with conferencing capability
peb 2445 overview semiconductor group 20 02.96 figure 8 shows the architecture of a primary access board with common channel signaling using four cmos devices. figure 8 architecture of a primary access board
peb 2445 overview semiconductor group 21 02.96 multipoint switching in a multipoint configuration the communication between different stations is done by using a common media. in a pbx system this can be achieved by connecting all stations to one (or more) time-slots and transmitting the information back. multipoint-switching is a special form of conferencing for data communication. in contrast to audio conferences terminals broadcast data to the musac-a which are only or-connected. that is, at each bit time, the conference sum is 1 if the input of one or more terminals is 1; otherwise, the result is 0. a simple example of such a system using siemens vlsi switching devices is shown in figure 9 . isdn subscribers are connected via line cards and pcm highways to a multipoint switching matrix. the data from different terminals are summed up in the multipoint switching matrix and transmitted back to all stations. the switching matrix is build by using just one musac-a. every combination of subscribers may be switched to the same transport media (time-slot), in this way enabling a number of powerful multipoint communication systems. figure 9 multipoint system configuration for isdn subscribers
peb 2445 overview semiconductor group 22 02.96 in order to establish a multipoint-connection with more than 64 terminals, you can form a multistage arrangement, as shown in figure 10 . figure 10 multistage arrangement
peb 2445 functional description semiconductor group 23 02.96 2 functional description figure 11 detailed block diagram of the peb 2445
peb 2445 functional description semiconductor group 24 02.96 2.1 basic functional principles the musac-a is a memory time switch device for a pcm pbx system, offering a variety of additional features like multipoint switching, conference calls, programmable noise suppression and attenuation. the musac-a works either in standard configuration for usual switching applications or in the primary access configuration, where it realizes, together with the peb 2035 (acfa) and the peb 2235 (ipat), the system interface for up to four primary multiplex access lines. in both configurations the conference and multipoint switching capability can be used. the block diagram is shown in figure 11 . the musac-a is designed to connect any of 512 pcm- input channels to any of 256 output channels. any input channel up to a total number of 64 can be handled in 21 independent conferences simultaneously. any conference combination from 3 subscribers in 21 conferences up to 64 subscribers in only one conference is possible. not more than 8 subscribers should be connected to a single conference, however, in order to ensure an acceptable speech quality. it can be improved by selecting an additional attenuation and activating the noise suppression: the input channels can be attenuated by 0, 3 db, 6 db or 9 db and the output channels by 0 or 3 db. input signals below a threshold programmable to four different levels are disregarded. the input information of a complete frame is stored in the on-chip 4-kbit speech memory (sm). the incoming 512 channels of 8 bits each are written in sequence into fixed positions in the sm with a repetition rate of 8 khz. additionally, in the second half of the frame the 64 conference output channels of 8 bit each are written into the sm. the memory access is normally controlled by the input counter in the timing control block when writing into the sm but by the conference unit when writing the conference output channels. the read access is independent of the write access, so that both input and conference output channels can be read at any time. for outputting, the connection memory (cm) is read in sequence. each location in the cm points to a location in the speech memory. before the byte in this sm location is read into the current output time-slot, it can be attenuated. the attenuation takes care of the compressed data format (a-law, m -law). the attenuations for all 256-output channels are stored in the cm and can be chosen between C 4 db (amplification) to 12 db (attenuation). the read access of the cm is controlled by the output counter also contained in the timing control block. in addition, in the first half of the frame the input channels connected to a conference are read in sequence by the conference unit (cu). all connections are set up by an external controller which programs the connection memory (cm) and the conference control memory (ccm) using the microprocessor interface. the cm address corresponds to one particular output time-slot and line number. the contents of this cm-location points to a particular input time-slot and line number in the transparent mode. in the conference mode or multipoint switching mode it contains the conference address and points to a conference output location in the sm instead. the same conference address is used to access the ccm. the parameters
peb 2445 functional description semiconductor group 25 02.96 stored in the ccm include the input time-slot and line number, the associated conference number as well as the noise suppression thresholds and the attenuation levels. the conference number defines a unique location in the conference sum memory (csm) used to store the accumulated samples for each conference. the conference sum memory is alternately loaded in the first half of the frame and unloaded in the following second half. in the first half the input samples are processed to implement the noise suppression, the expansion according to the european a-law or the us m -law and the attenuation function. the data memory (dm) buffers these samples for output processing. the csm is used to accumulate these samples and store the resulting sum. during output processing the input sample is retrieved from the data memory and the appropriate sum from the conference sum memory for subtraction, so that the channel output signal contains the contribution of all the other channels in the conference except its own. after output attenuation and pcm compression, the data are written in the speech memory for output switching. if one result of the subtractions exceeds the full scale value, a saturation appears and the musac-a signals this conference overflow condition by an interrupt. the conference number of the conference in overflow is buffered in the conference status register (cst) which can be retrieved by the external controller. a tone to be inserted into a conference is handled as an additional conference subscriber using any input pcm channel (access to ccm) but without assigning an output time-slot (no access to cm). multipoint switching is a special form of conferencing for data communication. in the multipoint switching mode several terminals are connected together. normally only one should transmit at a time; its signal is distributed to the other terminals. for collision detection purposes all input signals are summed up to construct the output signal. in contrast to audio conferences terminals broadcast data to the musac-a which are only or-connected. that is, at each bit time, the conference sum is 1 if the input of one or more terminals is 1; otherwise, the result is 0. the data memory, the subtractor, the linearization and attenuation are of no use in this mode. the general procedure is the same as for conferencing. all attenuations of the pcm values are calculated by the following mechanism 1. expansion according ccitt rec. g. 711 2. attenuation by lin. value 2 C (x/6) , x = attenuation 3. comparison according ccitt rec. g. 711 these functions are implemented by a pla/rom. the chip architecture makes it possible to decrease the delay between incoming and outgoing pcm channels. the processed input samples are transmitted either in the same frame or in the next frame at the latest.
peb 2445 functional description semiconductor group 26 02.96 definitions ? the peb 2445 works with either an 8192-khz clock or a 4096-khz clock. henceforth, the respective clock periods are referred to as t cp8 and t cp4 . ? the bits of a time-slot are numbered 0 through 7. bit 0 (msb) of a time-slot is the first bit to be received or transmitted by the musac-a, bit 7 (lsb) the last. preparation of the input data (input buffer) the peb 2445 works in 2048-, 4096- or 8192-kbit/s pcm systems. the frame frequency is 8000 hz in all 3 types of systems. therefore a frame consists of 32-, 64- or 128 time-slots of 1 byte each, respectively. in order to fill the speech memory, which has a fixed capacity of 512 channels, either 16-, 8- or 4 input lines are necessary, respectively. thus, in 4- and 8-mhz systems only some of the 16 input lines can be used. moreover, the peb 2445 can also work with two different input data rates simultaneously. in this case some of the pcm-input lines operate at one data rate, while others operate at another. table 2 states how many input lines are operating at the different data rates for all possible input data rate combinations. in the following they will be referred to as input modes. the input mode the peb 2445 is actually working in has to be programmed into the mode register, bits ml1, ml0, mo1, mo0. in chapter 4.1 you will find a complete description which input line is connected to which system, for each of the input modes. table 2 possible input modes the peb 2445 runs with either a 4096- or a 8192-khz device clock as selected with cfr:cps . data rates and clock frequencies may be combined freely. however, processing 8192-kbit/s data, an 8192-khz clock must be supplied. the preparation of the input data according to the selected input mode is made in the input buffer. it converts the serial data of a time-slot to parallel form. in standard configuration time-slot 0 begins with the rising edge of the sp pulse as shown in upper half of figure 12 denoted csr:(0000xxxx) . input modes type 16 2048 kbit/s single mode 8 4096 kbit/s single mode 4 8192 kbit/s single mode 2 8192 + 8 2048 kbit/s mixed mode 4 4096 + 8 2048 kbit/s mixed mode
peb 2445 functional description semiconductor group 27 02.96 as can be seen there the beginning of a input time-slot is defined such, that the input lines have settled to a stable value, when the datum is actually sampled. 4096- and 8192-kbit/s data is sampled in the middle of the bit period at the falling edge of the respective data clock. 2048-kbit/s data is sampled after 3/4 of the according bit period, i.e. with the rising edge of the 4 th 8192-khz clock cycle or the falling edge of the 2 nd 4096-khz clock cycle of the considered bit period. in the primary access configuration a different timing scheme may apply to the odd physical input lines. they are affected by the content of the clock shift register ( csr ), which can be programmed via the m p interface (see chapter 2.2 ). the clock shift register holds the information, how the frame structure is shifted in the primary access configuration. its content defaults to 00 h after power up and is also set to this value, whenever the standard configuration is selected.
peb 2445 functional description semiconductor group 28 02.96 figure 12 latching instant for input data
peb 2445 functional description semiconductor group 29 02.96 the four most significant bits of the clock shift register are of interest for the input lines. they only affect the odd input lines (see chapter 4.6.2 ): the frame structure can be advanced by the number of bit periods programmed to the rs2, rs1 and rs0 bits of the csr . for example, programming the csr with (1100xxxx) a new frame starts 6-bit periods before the rising edge of the sp pulse. selecting rre to logical 1 the frame is delayed by half a bit period (see figure 12 ). the data is then sampled in the middle of the respective bit period for all data rates. the last line of figure 12 shows the sampling instants for the csr entry (1001xxxx). then the input frame is advanced by 4-bit periods and delayed by a half resulting in an 3 1/2-clock period advancement of the input frame. for further examples refer to figure 20 . thus the frame structure may be selected to begin at any 1/2-bit period value between an resulting advancement of 7-bit periods and a resulting delay of 1/2 a bit period. setting csr =0x h the same timing conditions apply to even and odd inputs. then all system interface inputs are processed in the same way they are in the standard configuration. output buffer the output buffer rearranges the data read from the speech memory. it basically converts the parallel data to serial data. depending on the validity bit the output buffer outputs the data or switches the line to high impedance. the most significant bits of the 256 words in the connection memory are interpreted as validity bits for the 256 possible output channels: a logical 0 enables the programmed connection, a logical 1 tristates the output. the mode register ( mod ) bits ml1, ml0, mo1 and mo0 control this process. the possible output modes are listed in table 3 . table 3 possible output modes output modes type 8 2048 kbit/s single mode 4 4096 kbit/s single mode 2 8192 kbit/s single mode 1 8192 + 4 2048 kbit/s mixed mode 2 4096 + 4 2048 kbit/s mixed mode
peb 2445 functional description semiconductor group 30 02.96 figure 13 shows when the single bits are output. in standard configuration they are clocked off at the rising clock edge at the beginning of the considered bit period. time-slot 0 starts two t cp8 before the falling edge of the sp pulse. in primary access configuration the even output lines are affected by the xs2, xs1, xs0 and xfe entries in the clock shift register. the output frame is synchronized with the rising edge of the sp signal. assuming a csr entry x0 h the output frame starts with the rising edge of the sp pulse. programming the xs2, xs1 and xs0 bits with a value deviating from binary 000 the output frame is delayed by 8 d C (xs2, xs1, xs0) b bit periods. e.g, a csr entry of (xxxx0010) delays the output frame by 7-bit periods relative to the rising sp-pulse edge. programming csr:(xxxxxxx1) the output frame is delayed by another half a device clock period. in figure 13 the outputting instants are shown for a device clock of 4096 and 8192 khz and a csr:(xxxx0001) . the last line in figure 13 shows an even 8192-kbit/s output line for the csr entry (xxxx1101) and an 8192-khz device clock. the output frame is delayed by 2 1/2-bit periods. for further examples refer to figure 20 .
peb 2445 functional description semiconductor group 31 02.96 figure 13 clocking off instant of output data itd03747 56 7 bit0 1 2 3 4 5 6 7 0 1 2 3 t cp8 time slot 127 67 0 1 2 3 4 5 time slot 63 0 7 time slot 31 12 time slot 0 time slot 0 time slot 0 time slot 1 csr: (xxxx 0000) 2048 kbit/s data rate data rate 4096 kbit/s data rate 8192 kbit/s clk 4096 khz clk 8192 khz configuration standard configuration primary access sp sp 8192 kbit/s data rate 4096 kbit/s data rate data rate 2048 kbit/s time slot 1 time slot 0 time slot 0 time slot 0 1 time slot 31 70 time slot 63 4 3 2 1 0 7 6 time slot 127 2 1 0 7 6 5 4 3 2 1 bit0 7 6 5 67 0 1 2 3 4 time slot 63 0 7 time slot 31 1 time slot 0 time slot 0 2048 kbit/s data rate data rate 4096 kbit/s 56 7 bit0 1 2 3 4 5 6 7 0 time slot 127 time slot 0 data rate 8192 kbit/s 4 csr: (xxxx 1101) csr: (xxxx 0001) 4096 khz clock csr: (xxxx 0001) 8192 khz clock 2 4 2 - - - - - - - - - - - - - - -- - - - - - - - - - - - - -
peb 2445 functional description semiconductor group 32 02.96 configuration type the musac-a works either in the standard configuration for usual switching applications or in the primary access configuration. in these both configurations the conference and multipoint switching capability can be used. standard configuration a logical 1 in the cfs bit of the configuration register sets the peb 2445 in standard mode (default after power up). all modes from table 7 can be used. it has to be ensured that the data rate is not higher than the selected device clock (4096 or 8192 khz). in this application 512 channels per frame are written into the speech memory. each one of them can be connected to any output channel. any output channel can be attenuated independently of each other. according to table 8 and table 12 and depending on the selected mode the least significant bits of the connection memory address and data contain the logical pin numbers, the most significant bits the time-slot number of the output and input channels. the following example explains the programming sequence. time-slot 7 of the incoming 8192-kbit/s input line in 14 shall be connected to time-slot 6 of the output line out 5 of an 2048-kbit/s system. the attenuation for this connection should be 7 db. according to table 8 in 8192-kbit/s systems the input line in 14 is the logical input line 2. output line number and logical output number are identical to one another. according to chapter 4.5 c3 ? c0 is set to 7 h . therefore the following byte sequence on the address data bus has to be used to program the cm properly (see table 12 ): 01101100 (control byte) or 01011100 (control byte) 00011110 (data byte) 00011110 (data byte) 00110101 (address byte) 00110101 (address byte) the frame, for all input channels, starts with the rising edge of the sp signal. the frame for all output channels begins two t cp8 (with 8192-khz device clock) or one t cp4 period (4096-khz device clock) before the falling sp edge. the period of time between the rising and falling edge of the sp pulse should be t sph =(2 + n 4) t cp8 (0 n 255) =(1 + n 2) t cp4
peb 2445 functional description semiconductor group 33 02.96 n is an user defined integer. by varying n, t sph can be varied in 2048-khz clock period steps. for an example using n = 2 refer to figure 14 . figure 14 sp duration for n = 2 primary access configuration a logical 0 in the cfs bit of the configuration register selects the peb 2445 for primary access applications. in this case the musac-a is an interface device connecting a standard pcm interface (system interface) with another pcm interface e.g. an intermediate interface for connections to primary loops (synchronous interface). for both a serial interface is provided. the synchronous 2048-kbit/s interface consists of four input and four output lines with a bit rate of 2048-kbit/s. this interface can be used to connect the peb 2445 to up to four primary trunk lines via coding/decoding devices with frame alignment function (e.g. peb 2035 acfa) and line transceivers with clock and data recovery (e.g. peb 2235 ipat) and to signaling processors (e.g. the sab 82520 hscc). the system interface is not confined to one data rate but can operate at the full choice of the peb 2445 data rates: 2048, 4096 and 8192 kbit/s. a clock shift in a range of 7 1/2 clock steps with half clock step resolution may be programmed independently for inputs and outputs. the frame for all input- and output lines starts with the rising edge of the sp signal. in the primary access mode the signals tsc0 , tsc1 , tsc2 and tsc3 indicate when the associated system interface output is valid. the signal dcl supplies a 2-mhz clock which can be used for other devices at the synchronous interface, e.g. the high level serial communication controller hscc (sab 82520).
peb 2445 functional description semiconductor group 34 02.96 in the primary access configuration only those modes which support at least 4 input and 4 output lines at 2048 kbit/s can be used. these are the modes ml1, ml0, mo1, mo0 = 0 h , a h , f h (see table 7 ). programming the cm in the primary access configuration is described in tables 8, 13 and 14 . the attenuations are programmed in the same way as in the standard configuration. the least significant 2 bits of the data byte and the least significant bit of the address byte determine the type of interface, the more significant bits define the logical line number and time-slot number. according to figure 15 in the primary access configuration the connection memory is usually programmed to switch the system and synchronous interface inputs to the synchronous and system interface outputs, respectively. however, it is also possible to connect the system interface inputs to the system interface outputs as well as the synchronous interface inputs to the synchronous interface outputs. this connection possibility allows for test loops at the system and the synchronous interfaces. figure 15 connection choices in the primary access configuration
peb 2445 functional description semiconductor group 35 02.96 2.2 microprocessor interface and registers the musac-a is programmed via the m p interface. it consists of the address data bus ad7 ? ad0, the address bits a1 ? a0, the write (wr ), the read (rd ), the address latch enable (ale), the interrupt (int ) and the chip select (cs ) signal, as shown in figure 16 . figure 16 the musac tm -a controlled by a microprocessor the standard 8-bit m p interface can communicate with intel multiplexed/demultiplexed microprocessors. it gives access to the internal registers and to the control memories (connection memory, conference control memory). table 4 m p-interface functions ale is internally set to ground if it is not connected. for a demultiplexed m p interface the address bits a1 and a0 are needed for addressing a register. for the m p-interface timing please refer to chapter 5.3 . ale type of m p interface bus structure pin 24 pin 25 fixed to ground switching intel intel demultiplexed multiplexed rd rd wr wr
peb 2445 functional description semiconductor group 36 02.96 five directly addressable registers are provided: ? mode register (mod) ? status register (sta) ? conference status register (cst) ? conference mask register (cmr) ? indirect access register (iar) two other registers and the control memories are accessed by a simple three byte indirect access method: ? configuration register (cfr) ? clock shift register (csr) ? connection memory (cm) ? conference control memory (ccm) the status register (sta) and the conference status register (cst) are read-only- registers, the conference mask register (cmr) is a write-only-register; mod, cfr, csr, iar and cm or ccm can be read or written. an indirect access scheme is used to access the cfr, csr, cm or ccm using the indirect access register (iar). the following direct registers may be accessed: table 5 addressing the direct registers if a1 is not connected in the demultiplexed mode neither an access to the cmr, cst nor a read access to the mod register is possible. in this case a1 is fixed to ground internally. address write operation read operation demultiplexed mode a(1:0) multiplexed mode ad(7:0) 0 h 0 h mod sta 1 h 2 h iar iar 2 h 4 h cmr cst 3 h 6 h Cmod
peb 2445 functional description semiconductor group 37 02.96 indirect access to the cfr, csr, cm or ccm: an indirect access is performed by reading/writing three consecutive bytes (first byte = control byte, second byte = data byte, third byte = address byte) to/from iar. the control byte determines whether the cfr, the csr, the cm or the ccm shall be accessed, whether a write or read operation shall be performed and whether the first or the second memory access shall be executed. (to describe a conference two accesses to the ccm are necessary). the bits d7 ? d0 contain the information which shall be written into the control memories or the indirect registers. in the case of programming the cm the output attenuation is included either in the control byte (transparent switch) or in the data bits (conference switch). the address byte indicates which one of the indirect registers shall be accessed or in which memory location the data shall be written. an exact definition is given in chapter 4.5 . before an indirect access is started, the z- and b bits of the status register must be 0. with the first instruction the z bit is set (see chapter 4.2 ). after the third instruction the musac-a accesses the memory location. this access requires maximally 900 ns. after the access is finished the z bit is reset. figure 17 a) illustrates a write operation on the iar. it is possible to read or write the direct access registers while an indirect access is in progress. thus a register may be read in the time intervals that separate the three sequential indirect access instructions. also, the current indirect access may be aborted by setting the mod:ri. one indirect register access has to be completed before the next one can be started. to read the indirect registers or the cm two sequences of three instructions each have to be programmed. in the first sequence the musac-a is instructed which register or cm address to read. the data transferred to the peb 2445 in this first sequence is of no significance. with the first write instruction sta:z is set. after the first 3 instructions the musac-a needs 900 ns to write the result to the iar. the status register bit z is reset after maximally 900 ns. then 3 read operations follow. again, sta:z is set with the first read instruction. the 3 instructions read 3 bytes from the iar. figure 17 b) shows this procedure. after the third read operation the peb 2445 needs another 900 ns to reset the indirect access mechanism and the z bit in the status register. in ccm read accesses three sequences of three instructions (two identical write sequences and one read sequence; see figure17c) are necessary. bit 7 bit 0 c3 c2 k1 k0 c1 c0 d9 d8 control byte d7 d6 d5 d4 d3 d2 d1 d0 data byte ia7 ia6 ia5 ia4 ia3 ia2 ia1 ia0 address byte
peb 2445 functional description semiconductor group 38 02.96 figure 17 timing diagrams of iar
peb 2445 operational description semiconductor group 39 02.96 3 operational description 3.1 reset state after a hardware reset (res) or power up the musac-a is set to its initial state. the mod- and cfr register bits are all set to logical 1; the csr-, cst- and cmr-register bits are set to logical 0. the sta register b bit is undefined, the z bit contains logical 0. 3.2 initialization procedure after reset a few internal signals and clocks need to be initialized. this is done with the initialization sequence. to give all signals and clocks a defined value only 4 sp pulses are necessary. the sp pulses may be of any length allowed in normal application, the time interval between the two sp pulses may be of any length down to 250 ns. with all signals being defined, the cm needs to be reset. to do that a logical 0 is written into mod:rc. sta:b is set. the resulting cm reset is finished after max. 250 m s and is indicated by the status register b bit being logical 0. changing the pulse shaping factor n during cm reset may result in a cm-reset time longer than 250 m s. after resetting the cm, all bits in the cm are reset to 0, except for the d9-bit, which is set to one, causing the output lines to be tristated. to prepare the musac-a for programming the cm and ccm, the rl bit in the mode register must be reset. note that one mode register access can serve to reset both rc- and rl bits as well as configuring the chip (i.e. selecting operating mode etc.). figure 18 initializing the peb 2445 for a 8192-khz device clock
peb 2445 operational description semiconductor group 40 02.96 figure 19 initializing the peb 2445 for a 4096-khz device clock 3.3 operation with a 4096-khz device clock in order for the musac-a to operate with a 4096-khz device clock the cps bit in the cfr register needs to be reset. this has to be done before the cm reset and needs 1.8 m s. for a flow chart of this process refer to figure 19 . 3.4 standby mode with mod:sb being logical 1 the musac-a works as a backup device in redundant systems. it can be accessed via the m p interface and works internally like an active device. however, the outputs are high impedance. if the sb bit is reset, the outputs are switched to low impedance for the programmed active channels and this musac-a can take over from another device which has been recognized as being faulty.
peb 2445 detailed register description semiconductor group 41 02.96 4 detailed register description the following registers may be accessed: table 6 addressing the direct registers if a1 is not connected it is internally set to ground. in the demultiplexed mode neither an access to the cmr, cst nor a read access to the mod register is possible. the paragraphs in this section cover the registers in detail. 4.1 mode register (mod) access in the multiplexed m p-interface mode: write, address: 0 h read, address: 6 h access in the demultiplexed m p-interface mode: write, address: 0 h read, address: 0 h reset value: bf h rc reset connection memory; writing a zero to this bit causes the complete connection memory to be overwritten with 200 h (tristate). during this time sta:b is set. the maximum time for resetting is 250 m s. ri reset indirect access mechanism; setting this bit resets the indirect access mechanism. rl has to be cleared before writing/reading iar after reset. sb stand by ; by selecting sb = 1 all pcm outputs are tristated. the connection memory works normally. the musac-a can be activated immediately by resetting sb. mi1/0 input/output operation mode ; these bits define the bit rate of the input and mo1/0 output lines. the bitrates are given in table 7 , the corresponding pin functions in table 8 (standard configuration). address write operation read operation demultiplexed mode a(1:0) multiplexed mode ad(7:0) 0 h 0 h mod sta 1 h 2 h iar iar 2 h 4 h cmr cst 3 h 6 h Cmod ad7 ad0 rc 0 ri sb mi1 mi0 mo1 mo0
peb 2445 detailed register description semiconductor group 42 02.96 table 7 input/output operating modes mi1 mi0 mo1 mo0 input mode output mode 0 0 0 0 0 0 1 1 1 0 0 1 1 1 0 0 0 1 1 1 0 0 0 0 1 1 0 1 0 0 1 0 0 1 0 0 1 1 1 1 1 0 0 1 0 0 1 0 0 1 0 1 1 1 1 1 16 2 mbit/s 16 2 mbit/s 16 2 mbit/s 4 8 mbit/s 4 8 mbit/s 4 8 mbit/s 2 8 / 8 2 mbit/s 2 8 / 8 2 mbit/s 2 8 / 8 2 mbit/s 8 4 mbit/s 4 8 mbit/s 4 4 / 8 2 mbit/s 8 4 mbit/s 16 8 mbit/s 8 2 mbit/s 2) 2 8 mbit/s 4 2 / 1 8 mbit/s 8 2 mbit/s 2 8 mbit/s 4 2 / 1 8 mbit/s 8 2 mbit/s 2 8 mbit/s 4 2 / 1 8 mbit/s 2) 4 4 mbit/s 4 4 mbit/s 4 2 / 2 4 mbit/s 2) 2 8 mbit/s 2 8 mbit/s 1) 1 1 1 1 0 1 0 0 unused unused unused unused 1) for space switch application only; the conference or multipoint switching capability cannot be used in this operating mode 2) can also be used for primary access configuration note: in the mixed modes the first bit rate refers to the odd line numbers, the second one to the even line numbers.
peb 2445 detailed register description semiconductor group 43 02.96 input pin arrangement table 8 input and output pin arrangement for the standard configuration note: the input line numbers shown are the logical line numbers to be used for programming the connection memory and the conference control memory. in the case of 16 input lines the logical line numbers are identical to the pin names. output pin arrangement note: the logical output line numbers shown above are identical to the pin names. pin no. 16 8 mbit/s 16 2 mbit/s 4 8 mbit/s 8 2 + 2 8 mbit/s 8 4 mbit/s 8 2 + 4 4 mbit/s 4 5 7 8 9 10 11 12 13 14 15 16 17 18 19 20 in1 in0 in5 in4 in9 in8 in13 in12 in14 in15 in10 in11 in6 in7 in2 in3 in1 in0 in2 in3 in0 in4 in8 in1 in12 in14 in3 in10 in6 in2 in1 in0 in5 in4 in6 in7 in2 in3 in0 in4 in1 in8 in5 in12 in14 in7 in10 in3 in6 in2 pin no. 8 2 mbit/s 2 8 mbit/s 4 2 + 1 8 mbit/s 4 4 mbit/s 4 2 + 2 4 mbit/s 35 36 37 38 40 41 42 43 out7 out6 out5 out4 out3 out2 out1 out0 out1 out0 out7 out5 out3 out1 out0 out3 out2 out1 out0 out7 out5 out3 out2 out1 out0
peb 2445 detailed register description semiconductor group 44 02.96 table 9 input, output and tristate pin arrangement for the primary access configuration note: the input, output and tristate control line numbers shown in the center columns of this table are logical line numbers. the corresponding pin names are listed in the left most column. pin no. system interface mode pin name p-lcc 2 mhz 4 mhz 8 mhz tsc0 tsc1 tsc2 tsc3 5 8 10 12 tsc0 tsc1 tsc2 tsc3 tsc0 tsc1 tsc0 system interface tristate control signals, clock shift programmable out0 out2 out4 out6 43 41 38 36 out0 out1 out2 out3 out0 out1 out0 system interface outputs, clock shift programmable in13 in9 in5 in1 11 9 7 4 in3 in2 in1 in0 in1 in0 in0 system interface inputs, clock shift programmable out1 out3 out5 out7 42 40 37 35 out0 out1 out2 out3 out0 out1 out2 out3 out0 out1 out2 out3 synchronous 2-mhz interface outputs in14 in10 in6 in2 13 15 17 19 in3 in2 in1 in0 in3 in2 in1 in0 in3 in2 in1 in0 synchronous 2-mhz interface inputs mode 0000 1111 1010 mi1, mi0, mo1, mo0
peb 2445 detailed register description semiconductor group 45 02.96 4.2 status register (sta) access in the multiplexed m p-interface mode: read, address: 0 h access in the demultiplexed m p-interface mode: read, address: 0 h x dont care bbusy: the chip is busy resetting the connection memory (b = 1). b is undefined after power up and logical 0 after the device initialization. the three byte indirect access register is not accessible. note: the maximum time for resetting is 250 m s. z incomplete instruction; a three byte indirect instruction is not completed (z = 1). z is 0 after power up. note: z is reset and the indirect access is cancelled by setting mod:ri or resetting mod:rc. vn (3:0) version number according to the table below: 4.3 conference status register (cst) access in the multiplexed m p-interface mode: read, address: 4 h access in the demultiplexed m p-interface mode: read, address: 2 h reset value: 00 h xdont care ir initialization request . the connection memory and the conference control memory may have lost data (ir = 1). the ir bit is set after power failure or inappropriate clocking and is reset by reading cst. cov conference overflow (overflow t logical 1) cn4 ? cn0 conference number of the conference in overflow ad7 ad0 b z x x vn3 vn2 vn1 vn0 vn3 vn2 vn1 vn0 device versions 1 000a1 1 001v 1.2 ad7 ad0 x ir cov cn4 cn3 cn2 cn1 cn0
peb 2445 detailed register description semiconductor group 46 02.96 4.4 conference mask register (cmr) access in the multiplexed m p-interface mode: write, address: 4 h access in the demultiplexed m p-interface mode: write, address: 2 h reset value: 00 h a logical 1 disables the corresponding interrupt. ir initialization request mask; the initialization request is masked (ir = 1) cov conference overflow mask; the conference overflow is masked (cov = 1) 4.5 indirect access register (iar) access in the multiplexed m p-interface mode: read/write, address: 2 h access in the demultiplexed m p-interface mode: read/write, address: 1 h an indirect access is performed by reading/writing three consecutive bytes (first byte = control byte, second byte = data byte, third byte = address byte) to/from iar. k1, k0 control the indirect access according to the following table c3 C c0 additional programming bits x = dont care; C is not needed to define type of access ad7 ad0 0ircov00000 bit 7 bit 0 c3 c2 k1 k0 c1 c0 d9 d8 control byte d7 d6 d5 d4 d3 d2 d1 d0 data byte ia7 ia6 ia5 ia4 ia3 ia2 ia1 ia0 address byte k1, k0 c3 C c0 d8 type of access 00 10/01 11 x h 0 h , 2 h 4 h Cf h 1 h , 3 h 4 h 6 h 8 h a h 0 h 0 h C C C C C C C 0 1 read cm write cm: transp. switch, att. value programmable with c3 c0 write cm: conf. switch, att. value programmable with d8 C d6 write ccm, first access read ccm, first access write ccm, second access read ccm, second access write indirect register read indirect register
peb 2445 detailed register description semiconductor group 47 02.96 attenuation table 10 transparent switching table 11 conference switching c3 ? c0 attenuation 0 h a h 2 h b h 4 h 5 h 6 h 7 h 8 h 9 h f h e h d h c h 0db 1db 2db 3db 4db 5db 6db 7db 8db 10 db 12 db C2db C3db C4db c3 ? c0 d8 C d6 attenuation 1 h 3 h 0 h 1 h 1) 2 h 3 h 1) 4 h 5 h 6 h 7 h 0 h 1 h 2 h 3 h 4 h 5 h 6 h 7 h 0db C 2db C 4db 5db 6db 7db 8db 10 db 1db 3db C4db C3db C2db 12 db 1) may not select
peb 2445 detailed register description semiconductor group 48 02.96 access to cm transparent switching (i.e. the musac-a works exactly like a mtsc) c3 ? c0 = 0 h , 2 h , 4 h Cf h d9 validity bit: a logical 0 enables the programmed connection, a logical 1 tristates the outputs d8 ? d0 logical line and time-slot number of the inputs ia7 ? ia0 logical line and time-slot number of the outputs c3 ? c0, is written to the cm address ia7 C ia0 d9 C d0 conference switching or multipoint switching mode c3 ? c0=1 h , 3 h d9 validity bit: a logical 0 enables the programmed connection, a logical 1 tristates the outputs d8 ? d6 output attenuation d5 ? d0 conference control address ia7 ? ia0 logical line and time-slot number of the outputs c3 ? c0, is written to the cm address ia7 C ia0. d5 C d0 contain the address d9 C d0 which points to the appropriate ccm location. d8 C d0 and ia7 C ia0 contain the information for the logical line and time-slot numbers of the programmed connection, d8 C d0 for the inputs, ia7 C ia0 for the outputs. table 12 shows the programming of these bits for standard configuration, table 13 and 14 for the primary access configuration.
peb 2445 detailed register description semiconductor group 49 02.96 standard configuration table 12 time-slot and line programming for standard configuration standard configuration, all modes except space switch mode 2-mbit/s input lines bit d3 to d0 bit d8 to d4 bit d9 logical line number time-slot number validity bit 4-mbit/s input lines bit d2 to d0 bit d8 to d3 bit d9 logical line number time-slot number validity bit 8-mbit/s input lines bit d1 to d0 bit d8 to d2 bit d9 logical line number time-slot number validity bit 2-mbit/s output lines bit ia2 to ia0 bit ia7 to ia3 line number time-slot number 4-mbit/s output lines bit ia1 to ia0 bit ia7 to ia2 line number time-slot number 8-mbit/s output lines bit ia0 bit ia7 to ia1 line number time-slot number
peb 2445 detailed register description semiconductor group 50 02.96 primary access configuration table 13 time-slot and line programming for the primary access configuration 2-mbit/s input lines bit d1 to d0 bit d3 to d2 bit d8 to d4 bit d9 interface select in line number time-slot number validity bit 4-mbit/s input lines bit d1 to d0 bit d2 bit d8 to d3 bit d9 fixed to 01 (system interface) time slot number time-slot number validity bit 8-mbit/s input lines bit d1 to d0 bit d8 to d2 bit d9 fixed to 01 (system interface) time slot number validity bit 2-mbit/s output lines bit ia0 bit ia2 to ia1 bit ia7 to ia3 interface select out line number time-slot number 4-mbit/s output lines bit ia0 bit ia1 bit ia7 to ia2 fixed to 0 (system interface) line number time-slot number 8-mbit/s output lines bit ia0 bit ia7 to ia1 fixed to 0 (system interface) time-slot number
peb 2445 detailed register description semiconductor group 51 02.96 the interface select bits have to be programmed as shown in the following table: table 14 interface selection bits access 1 to ccm c3 ? c0 logical 4 h , 6 h d9 inversion bit: in a multiparty conference there is some risk of instability due to reflections at the hybrid. if these reflections are not cancelled, they will be summed up in the conference sum and will be transmitted to the subscriber, where again they could be reflected. in very big conferences (>> 4 subscribers) this behaviour could result in an instability. to avoid this the peb 2445 has the ability to invert every second conference channel, which has no audible influence on the speech quality. by this the noise due to reflections is compensated to a high degree. the feature can also be applied to reduce noise due to line impedence mismatch. d8 ? d0 logical line and time-slot number of the inputs (see table 12, 13 and 14 ) ia7/ia6 logical 0 ia5 ? ia0 conference control address access 2 to ccm c3 ? c0 logical 8 h , a h d9/d8 noise suppression threshold d7/d6 input attenuation level d5 output attenuation level note: d7, d6, d5 are only relevant to conference mode; in the multipoint switching mode these bits must be logical 0. d4 ? d0 conference number: 21 independent simultaneous conferences are possible. by using the conference number 1f h an attenuation or noise suppression can be inserted in a channel without conferencing. ia7/ia6 logical 0 ia5 ? ia0 conference control address system interface synchronous 2-mhz interface input lines 01 10 output lines 0 1
peb 2445 detailed register description semiconductor group 52 02.96 table 15 table 16 table 17 note: the sequence of programming (access 1, access 2) is important. d9 d8 noise suppression threshold 0 0 no noise suppression 0 1 fifth step, first segment 1 0 ninth step, first segment 1 1 sixteenth step, first segment d7 d6 input attenuation level 000 db 013 db 106 db 119 db d5 output attenuation level 00 db 13 db
peb 2445 detailed register description semiconductor group 53 02.96 4.6 indirect registers 4.6.1 configuration register (cfr) access: read or write at address fe h reset value: ff h cps clock period select: device clock is set to 8192 khz (logical 1) or 4096 khz (logical 0). cfs configuration select: the musac-a works either in the primary access configuration (cfs = 0) or in the standard configuration (cfs = 1). fs function select: fs = 0: multipoint switching fs = 1: conferencing cua0 ? cua2 pcm encoding law and pcm-byte format ad7 ad0 1 1 cua2 cua1 cua0 fs cfs cps cua0 encoding law 1 a-law 0 m -law cua2 cua1 pcm-byte format 0 0 no bits inverted 0 1 even bits inverted 1 0 odd bits inverted 1 1 all bits inverted
peb 2445 detailed register description semiconductor group 54 02.96 4.6.2 clock shift register (csr) access: read or write at address ff h reset value: 00 h rs2 ? rs0 receive clock shift , bits 2 C 0. the received data stream is shifted in bit period steps. rre receive with rising edge . the data is sampled with the falling (rre = 0) or rising edge (rre = 1) of the data equivalent clock. xs0 ? xs2 transmit clock shift , bits 2 C 0. the transmitted data stream is shifted. xfe transmit with falling edge ; data is transmitted with the rising (xfe = 0) or falling edge (xfe = 1) of the device clock. data stream manipulation according to these register entries only affects the system interface and only in the primary access configuration. the frame structure can be moved relative to the sp slope by up to 7 clock periods in half clock period steps. this register can hold non-zero values only for a cfr:cfs value of logical 0. identical non-zero entries for rs2 C rs0 and xs2 C xs0 as well as identical rre and xfe generate an output time-slot structure which is 1 time-slot late relative to the input time-slot structure. identical 000 entries for rs2 C rs0 and xs2 C xs0 as well as rre and xfe being logical 0 cause the input and output frames to coincide in time. ad7 ad0 rs2 rs1 rs0 rre xs2 xs1 xs0 xfe
peb 2445 detailed register description semiconductor group 55 02.96 figure 20 clock shifting
peb 2445 electrical characteristics semiconductor group 56 02.96 5 electrical characteristics note: stresses above those listed here may cause permanent damage to the device. exposure to absolute maximum rating conditions for extended periods may affect device reliability. maximum ratings are absolute ratings; exceeding only one of these values may cause irreversible damage to the integrated circuit. 5.1 dc characteristics t a = 0 to 70 c; v dd = 5 v 5 %, v ss = 0 v note: the listed characteristics are ensured over the operating range of the integrated circuit. typical characteristics specify mean values expected over the production spread. if not otherwise specified, typical characteristics apply at t a = 25 c and the given supply voltage. absolute maximum ratings parameter symbol limit values unit ambient temperature under bias: peb t a 0 to 70 c storage temperature t stg - 65 to 125 c voltage on any pin with respect to ground v s - 0.4 to v dd + 0.4 v maximum voltage on any pin v max 7v parameter symbol limit values unit test condition min. max. l-input voltage v il - 0.4 0.8 v h-input voltage v ih 2.0 2.7 v dd + 0.4 v dd + 0.4 clk and wr only l-output voltage v ol 0.45 v i ol = 2 ma h-output voltage h-output voltage v oh v oh 2.4 v dd - 0.5 v v i oh = - 400 m a i oh = - 100 m a power supply current operational clk = 4 mhz clk = 8 mhz i cc i cc 5 10 ma ma v dd = 5 v, inputs at 0 v or v dd , no output loads input leakage current output leakage current i li i lo 10 m a0 v < v in < v dd to 0 v 0 v < v out < v dd to 0 v input leakage current at inputs with internal pull- down i lpd 700 m a0 v < v in < v dd to 0 v res, ale, a0, a1 only
peb 2445 electrical characteristics semiconductor group 57 02.96 5.2 capacitances t a = 25 c; v dd = 5 v 5 %, v ss = 0 v 5.3 ac-characteristics ambient temperature under bias range, v dd = 5 v 5 %. inputs are driven to 2.4 v for a logical 1 and to 0.4 v for a logical 0. timing measurements are made at 2.0 v for a logical 1 and at 0.8 v for a logical 0. the ac-testing input/output wave forms are shown below. figure 21 i/o-wave form for ac-test 5.3.1 microprocessor interface timing 5.3.1.1 intel bus mode figure 22 m p read cycle parameter symbol limit values unit min. max. input capacitance c in 10 pf output capacitance c out 15 pf i/o c i/o 20 pf under device test its05853 = 150 pf c l 2.4 v 0.4 v test points 2.0 v 0.8 v 0.8 v 2.0 v
peb 2445 electrical characteristics semiconductor group 58 02.96 figure 23 m p write cycle figure 24 multiplexed address timing figure 25 non-multiplexed address timing
peb 2445 electrical characteristics semiconductor group 59 02.96 table 18 microprocessor interface timing 5.3.2 pcm interface timing table 19 pcm interface timing parameter symbol limit values unit test condition min. max. ale pulse width t aa 50 CnsC address setup time to ale t al 20 C ns C address hold time from ale t la 10 C ns C address latch setup time to wr , rd t als 0CnsC address setup time to wr , rd t as 10 C ns C address hold time from wr , rd t ah 20 C ns C ale pulse delay t ad 15 C ns C rd pulse width t rr 110 C ns C data output delay from rd t rd C 110 ns C data float from rd t df C25nsC rd control interval t ri 70 C ns C wr pulse width t ww 60 C ns C data setup time to wr + cs t dw 35 ns C data hold time from wr + cs t wd 20 C ns C wr control interval t wi 70 C ns C parameter symbol limit values unit min. max. pcm input setup t s 15 C ns pcm input hold t h 30 C ns output delay t d C45ns tristate delay t t C66ns
peb 2445 electrical characteristics semiconductor group 60 02.96 5.3.3 clock and synchronization timing table 20 pcm interface timing parameter symbol limit values unit min. max. clock period 8 mhz high t cp8h 40 Cns clock period 8 mhz low t cp8l 48 C ns clock period 8 mhz t cp8 120 C ns synchronization pulse setup 8 mhz t ss8 20 t cp8 - 20 ns synchronization pulse delay 8 mhz t sh8 0 t cp8 - 20 ns clock period 4 mhz high t cp4h 90 C ns clock period 4 mhz low t cp4l 90 C ns clock period 4 mhz t cp4 240 C ns synchronization pulse setup 4 mhz t ss4 20 t cp4 - 30 ns synchronization pulse delay 4 mhz t sh4 30 t cp4 - 10 + t cp4h ns data clock delay t dcd C100ns synchronization pulse low t spl 100 C ns
peb 2445 electrical characteristics semiconductor group 61 02.96 figure 26 pcm line timing in standard configuration with a 8 mhz device clock
peb 2445 electrical characteristics semiconductor group 62 02.96 figure 27 pcm line timing in primary access configuration with a 8 mhz device clock and a csr entry (00010001)
peb 2445 electrical characteristics semiconductor group 63 02.96 figure 28 pcm line timing in standard configuration with a 4 mhz device clock
peb 2445 electrical characteristics semiconductor group 64 02.96 figure 29 pcm line timing in primary access configuration with a 4 mhz device clock and a csr entry (00010001)
peb 2445 package outlines semiconductor group 65 02.96 6 package outlines p-lcc-44 (smd) (plastic leaded chip carrier) gpl05102 md = surface mounted device sorts of packing package outlines for tubes, trays etc. are contained in our data book package information. dimensions in mm
peb 2445 appendix semiconductor group 66 02.96 7 appendix 7.1 initialization for conferencing in a pbx 1) see table 7 2) see table 8
peb 2445 appendix semiconductor group 67 02.96 7.2 programming a conference in a pbx figure 30 table 21 procedure for each conference bits in iar values for subscribers te a te b te c 1. make a list of the conference subscribers 2. determine the input time slot determine the logical input port its6 ? 0 l3 ? 0 3. determine the output time slot determine the logical output port ots6 ? 0 ol2 ? 0 4. find an unused conference number cnr4 ? 0 5. assign an unused conference control address to every conference input cca5 ? 0 6. fix the input attenuation iat1 ? 0 7. fix the output attenuation oat, oat4 ? 0 8. fix the noise suppression threshold noi1 ? 0 9. insert the determined values in the corresponding bit positions of the musac-a work sheet (see chapter 7.3 and 7.4 ). write the 9 bytes to the cm and ccm using the three byte iar access.
peb 2445 appendix semiconductor group 68 02.96 7.3 programming procedure for switching tss C select a column for input and output rate C fill in the values of the bits C write the 3 bytes (from top to bottom) to register iar its6 ? 0 il0 ? 3 input time slot number logical input line number val validity: output enabled (= 0) output disabled (= 1) ots6 ? 0 output time slot ol2 ? 0 logical output line number oat3 ? 0 output attenuation: 0 h = 0 db a h = 1 db 2 h = 2 db b h = 3 db 4 h = 4 db 5 h = 5 db 6 h = 6 db 7 h = 7 db 8 h = 8 db 9 h = 10 db f h = 12 db e h = - 2 db d h = - 3 db c h = - 4 db 2 mbit/s output rate 4 mbit/s output rate 8 mbit/s output rate 3 byte iar access to cm: iar oat3 ? 2 oat1 ? 0 1 0 val its4 iar oat3 ? 2 oat1 ? 0 1 0 val its5 iar oat3 ? 2 oat1 ? 0 1 0 val its6 iar its3 ? 0 il3 ? 0 iar its4 ? 0 il2 ? 0 iar its5 ? 0 il1 ? 0 iar ots4 ? 0 ol2 ? 0 iar ots5 ? 0 ol1 ? 0 iar ots6 ? 0 ol0
peb 2445 appendix semiconductor group 69 02.96 7.4 programming procedure for a pbx conference C select a column for input and output rate C fill in the values of the bits by aid of chapter 7.1 and 7.2 C write the 9 bytes (from top to bottom) to register iar iar inv its4 2 mbit/s input rate 4 mbit/s input rate 8 mbit/s input rate first 3 byte iar access to ccm: 0 1 1 1 0 0 iar inv its5 0 1 1 1 0 0 iar inv its6 0 1 1 1 0 0 iar its3 ? 0 il3 ? 0 iar its5 ? 0 il1 ? 0 iar its4 ? 0 il2 ? 0 iar 0 cca5 ? 0 0 iar 1 0 1 1 0 0 noi1 ? 0 iar iat1 ? 0 oat cnr4 ? 0 iar 0 cca5 ? 0 0 second 3 byte iar access to ccm: 2 mbit/s output rate 4 mbit/s output rate 8 mbit/s output rate 3 byte iar access to cm: iar ots5 ? 0 ol1 ? 0 iar ots4 ? 0 ol2 ? 0 iar 0 0 1 0 val oat 2 oat4 ? 3 iar oat1 ? 0 cca5 ? 0 iar ots6 ? 0 ol0
peb 2445 appendix semiconductor group 70 02.96 inv pcm data inverted (= 1) or not (= 0) its6 ? 0 input time slot number il0 ? 3 logical input line number cca5 ? 0 conference control address noi1 ? 0 noise suppression threshold: 00 = no noise suppression 01 = 5 th step, first segment 10 = 9 th step, first segment 11 = 16 th step, first segment iat1 ? 0 input attenuation: 00 = 0 db 01 = 3 db 10 = 6 db 11 = 9 db cnr4 ? 0 conference number val validity: output enabled (= 0) output disabled (= 1) ots6 ? 0 output time slot ol2 ? 0 logical output line number oat output attenuation: 0=0db, 1=3db oat4 ? 0 output attenuation: 01000 = 0 db 01111 = 7 db 11010 = 1 db 11000 = 8 db 01010 = 2 db 11001 = 10 db 11011 = 3 db 11111 = 12 db 01100 = 4 db 11100 = - 4 db 01101 = 5 db 11101 = - 3 db 01110 = 6 db 11110 = - 2 db other bit combinations not allowed!

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